Alpha CPU-specific builtins

[Aldy Hernandez]

>>>>> "Falk" == Falk Hueffner <falk.hueffner@student.uni-tuebingen.de> writes:

 > x.c:1: unrecognizable insn:
 > (insn 32 13 15 (set (reg:V8QI 2 $2)
 >         (const_vector:V8QI[ 
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >                 (const_int 0 [0x0])
 >             ] )) -1 (nil)
 >     (nil))

add a pattern to clear a vector register, probably with an xor.
you'll need one eventually.

see the ppc pattern:

(define_insn "*movv16qi_const0"
  [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
	(match_operand:V16QI 1 "zero_constant" ""))]
  "TARGET_ALTIVEC"
  "vxor %0,%0,%0"
  [(set_attr "type" "vecsimple")])

ideally though, you should be generating all this from your "movv8qi"
pattern.

...assuming this instruction should be generated in the first place.

aldy