Alpha CPU-specific builtins

[Falk Hueffner]

Richard Henderson <rth@redhat.com> writes:

> reg_or_0_operand should use CONST0_RTX (mode) instead of const0_rtx.
> Also, PREDICATE_CODES for reg_or_0_operand should be extended to
> include CONST_DOUBLE and CONST_VECTOR.

OK, I did that. Now for the same example __builtin_alpha_minub8(0, a),
I get:

x.c:1: unrecognizable insn:
(insn 32 13 15 (set (reg:V8QI 2 $2)
        (const_vector:V8QI[ 
                (const_int 0 [0x0])
                (const_int 0 [0x0])
                (const_int 0 [0x0])
                (const_int 0 [0x0])
                (const_int 0 [0x0])
                (const_int 0 [0x0])
                (const_int 0 [0x0])
                (const_int 0 [0x0])
            ] )) -1 (nil)
    (nil))
x.c:1: Internal compiler error in extract_insn, at recog.c:2133

I've added this to alpha.h:

#define VECTOR_MODE_SUPPORTED_P(MODE) \
  (TARGET_MAX \
   && ((MODE) == V8QImode || (MODE) == V4HImode))

and tried adding a pattern like this:

(define_expand "movv8qi"
  [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
        (match_operand:V8QI 1 "general_operand" ""))]
  ""
{
  emit_something...
  DONE;
})

but it doesn't get triggered at all... I suspect I'm missing something
obvious here,any hints?

-- 
	Falk