Fwd: Questions on PA machine description?

[Jeffrey A Law]

  In message < 19990319173226.C14722@cygnus.com >you write:
  > Does it seem worthwhile to add some sort of target define to control
  > adding dependant insns to the ready queue in the same cycle?  It's
  > true that it doesn't matter to the vast majority of the processors
  > we support, but I'm thinking of VLIW parts that do actually have
  > write-after-read conflicts within a cycle.
That's basically what I've had in mind.  In addition to checking the
target macro, I think we'd want to check the ready delay and only do
this if it's zero.

I hadn't even thought about the VLIW issues, but yea, it seems like we'd
want to have the same kind of capability for VLIW targets.

jeff