Fwd: Questions on PA machine description?

[Richard Henderson]

On Thu, Mar 18, 1999 at 10:00:20PM -0700, Jeffrey A Law wrote:
> It has a structure like:
> 
> while (not all insns scheduled)
>   add insns with no outstanding dependencies to the ready queue
>   sort the ready queue
>   while (ready list is not empty && target can issue more insns)
>     issue an insn off the ready queue, remove dependencies on the issued insn
> 
> So, given insn1 which feeds insn2 we will never issue insn1 & insn2 in the
> same cycle.

I noticed this the other day in a different context. 

Does it seem worthwhile to add some sort of target define to control
adding dependant insns to the ready queue in the same cycle?  It's
true that it doesn't matter to the vast majority of the processors
we support, but I'm thinking of VLIW parts that do actually have
write-after-read conflicts within a cycle.


r~