Pentium and second pipeline

[Joern Rennecke]

> Another idea I got is to define two units (integeru and integerv)
> and set some colision between (as far as I know, imul blocks both units)
> but don't have any idea, if two units accepting same sort of instructions are
> alowed and how will scheduler handle this.

More straightforward is to define a special function unit that represents
the dpecial capabilities of the u pipeline, and mark only those instructions
that can only be executed in the u pipeline as using that unit.