PRECISE gcc Intel conventions

[Nick Maclaren]

Is there anything on the PRECISE gcc Intel conventions?  In this
context, I need to know exactly which registers and flags are
used for what and what the constraints are.  And that doesn't
mean just the visible ones, but the invisible ones, and any memory
locations used for stack linkage, state control etc.

What I am looking at is proper, mainframe-style exception handling,
which involves reverse engineering the stack frame that was
interrrupted and hooking the subsequent calls into it seamlessly.
I have done that, but it was under MVS on a System/370, and have
dabbled with a few other systems.  It is NOT easy and is NOT done
by any current Unix/Microsoft system I know of.

It isn't practical to reverse engineer this in a feasible amount
of time, as you can never check what you haven't thought of.  The
information must exist, but it may not be written down.


Regards,
Nick Maclaren,
University of Cambridge Computing Service,
New Museums Site, Pembroke Street, Cambridge CB2 3QH, England.
Email:  nmm1@cam.ac.uk
Tel.:  +44 1223 334761    Fax:  +44 1223 334679