[gcc(refs/users/meissner/heads/work235-sha)] PR target/117251: Improve vector andc to vector andc fusion

[Michael Meissner]

https://gcc.gnu.org/g:125f6f684ebeb4f02d065ee42edace1170db7ce8

commit 125f6f684ebeb4f02d065ee42edace1170db7ce8
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Jan 30 16:45:01 2026 -0500

    PR target/117251: Improve vector andc to vector andc fusion
    
    See the following post for a complete explanation of what the patches
    for PR target/117251:
    
     * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
    
    This is patch #8 of 45 to generate the 'XXEVAL' instruction on power10
    and power11 instead of using the Altivec 'VANDC' instruction feeding
    into 'VANDC'.  The 'XXEVAL' instruction can use all 64 vector
    registers, instead of the 32 registers that traditional Altivec vector
    instructions use.  By allowing all of the vector registers to be used,
    it reduces the amount of spilling that a large benchmark generated.
    
    Currently the following code:
    
            vector int a, b, c, d;
            a = (c & ~ d) & ~ b;
    
    Generates:
    
            vandc  t,c,d
            vandc  a,t,b
    
    Now in addition with this patch, if the arguments or result is
    allocated to a traditional FPR register, the GCC compiler will now
    generate the following code instead of adding vector move instructions:
    
            xxeval a,b,c,13
    
    Since fusion using 2 Altivec instructions is slightly faster than using
    the 'XXEVAL' instruction we prefer to generate the Altivec instructions
    if we can.  In addition, because 'XXEVAL' is a prefixed instruction, it
    possibly might generate an extra NOP instruction to align the 'XXEVAL'
    instruction.
    
    I have tested these patches on both big endian and little endian
    PowerPC servers, with no regressions.  Can I check these patchs into
    the trunk?
    
    2026-01-30  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
            to generate vector/vector andc/andc fusion if XXEVAL is
            supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 595217ed7c83..6b283c2f29e1 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2054,20 +2054,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vandc -> vandc
 (define_insn "*fuse_vandc_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
-                          (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
-                 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+                          (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+                 (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vandc %3,%1,%0\;vandc %3,%3,%2
    vandc %3,%1,%0\;vandc %3,%3,%2
    vandc %3,%1,%0\;vandc %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,13
    vandc %4,%1,%0\;vandc %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector veqv -> vandc
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index da33b402e10e..53021a8005b7 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -222,6 +222,7 @@ sub gen_logical_addsubf
       "vnor_vand"   =>   8,
       "veqv_vand"   =>   9,
       "vorc_vand"   =>  11,
+      "vandc_vandc" =>  13,
     );
 
     KIND: foreach $kind ('scalar','vector') {