[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121485] Fix mode on Zvkned lmul extending patterns

[Jeff Law]

https://gcc.gnu.org/g:addb12aca5fcdf8b852117dba2c64c11a38a0e43

commit addb12aca5fcdf8b852117dba2c64c11a38a0e43
Author: Jeff Law <jeffrey.law@oss.qualcomm.com>
Date:   Tue Dec 30 22:52:03 2025 -0700

    [RISC-V][PR target/121485] Fix mode on Zvkned lmul extending patterns
    
    This fixes the mode on the lmul-extending variants of various Zvkned patterns.
    
    Essentially vsetvl insertion depends on the mode of each insn and for lmul
    extending patterns, we need the larger mode, not the smaller one to get the
    correct vsetvls.
    
    Tested on riscv{32,64}-elf on the simple testcase in the PR.  I also verified
    the larger testcase in godbolt appears to work correctly.
    
    Waiting on upstream CI before committing.
    
            PR target/121485
    gcc/
            * config/riscv/vector-crypto.md: Fix mode attribute for the
            lmul extending Zvkned patterns.
    
    gcc/testsuite/
            * gcc.target/riscv/rvv/vsetvl/pr121485.c: New test.
    
    (cherry picked from commit 5d3874416c5eb09d2de3d9bfa1f22f537c3384e2)

Diff:
---
 gcc/config/riscv/vector-crypto.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
index 5579b56a27f9..cd2e88072751 100644
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -538,7 +538,7 @@
   "TARGET_ZVKNED || TARGET_ZVKSED"
   "v<vv_ins_name>.<ins_type>\t%0,%2"
   [(set_attr "type" "v<vv_ins_name>")
-   (set_attr "mode" "<VSIX2>")])
+   (set_attr "mode" "<V_VLSI_S_X2>")])
 
 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar"
  [(set (match_operand:<V_VLSI_S_X4> 0 "register_operand"      "=&vr")
@@ -556,7 +556,7 @@
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<VSIX4>")])
+  (set_attr "mode" "<V_VLSI_S_X4>")])
 
 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar"
  [(set (match_operand:<V_VLSI_S_X8> 0 "register_operand"      "=&vr")
@@ -574,7 +574,7 @@
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<VSIX8>")])
+  (set_attr "mode" "<V_VLSI_S_X8>")])
 
 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar"
  [(set (match_operand:<V_VLSI_S_X16> 0 "register_operand"      "=&vr")
@@ -592,7 +592,7 @@
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<VSIX16>")])
+  (set_attr "mode" "<V_VLSI_S_X16>")])
 
 ;; vaeskf1.vi vsm4k.vi
 (define_insn "@pred_crypto_vi<vi_ins_name><mode>_scalar"