[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Fix slide pattern recognition [PR122124]

[Jeff Law]

https://gcc.gnu.org/g:d3cb920ceee6562204ff312e4f7fd41397219c84

commit d3cb920ceee6562204ff312e4f7fd41397219c84
Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
Date:   Tue Oct 7 07:14:01 2025 -0600

    [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
    
    Ensure the second pivot is really a pivot and it's not in OP1.
    
            PR target/122124
    gcc/ChangeLog:
            * config/riscv/riscv-v.cc (shuffle_slide_patterns): Check if
            the second pivot is in OP1 and improve comments.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/rvv/autovec/pr122124.c: New test.
    
    (cherry picked from commit 34ef2eec90baff5a7b84806fb0c7a5cef16b5350)

Diff:
---
 gcc/config/riscv/riscv-v.cc                         |  5 +++--
 .../gcc.target/riscv/rvv/autovec/pr122124.c         | 21 +++++++++++++++++++++
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 31dd4dc65956..70f02fd01537 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3779,14 +3779,15 @@ shuffle_slide_patterns (struct expand_vec_perm_d *d)
   int pivot = -1;
   for (int i = 0; i < vlen; i++)
     {
+      /* The first pivot is in OP1.  */
       if (pivot == -1 && known_ge (d->perm[i], vec_len))
 	pivot = i;
       if (i > 0 && i != pivot
 	  && maybe_ne (d->perm[i], d->perm[i - 1] + 1))
 	{
-	  if (pivot == -1 || len != 0)
+	  /* A second pivot would indicate the vector length and is in OP0.  */
+	  if (known_ge (d->perm[i], vec_len) || pivot == -1 || len != 0)
 	    return false;
-	  /* A second pivot would indicate the vector length.  */
 	  len = i;
 	}
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122124.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122124.c
new file mode 100644
index 000000000000..29d51b618548
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122124.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-O0 -std=gnu99" } */
+
+#include <stdint.h>
+#include <stdio.h>
+#define BS_VEC(type, num) type __attribute__((vector_size(num * sizeof(type))))
+uint16_t func_24() {
+  BS_VEC(uint32_t, 4) zero = {0};
+  BS_VEC(uint8_t, 2)
+  BS_VAR_1 = __builtin_shufflevector(
+      (BS_VEC(uint8_t, 4))5,
+      __builtin_convertvector(zero, BS_VEC(uint8_t, 4)), 5, 0);
+  return BS_VAR_1[1];
+}
+int main() {
+  printf("%u\n", func_24());
+}
+
+/* { dg-output "5" } */