[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add missing define_insn_reservation to tt-ascalon-d8.md [PR121982]

[Jeff Law]

https://gcc.gnu.org/g:a51a5b6ab5ac05b58afea5e96501be456b9b151e

commit a51a5b6ab5ac05b58afea5e96501be456b9b151e
Author: Peter Bergner <bergner@tenstorrent.com>
Date:   Mon Sep 22 12:17:26 2025 -0500

    RISC-V: Add missing define_insn_reservation to tt-ascalon-d8.md [PR121982]
    
    The tt-ascalon-d8's pipeline description has reservations for 16-bit, 32-bit
    and 64-bit vector integer divides, but was missing a reservation for 8-bit
    vector integer divides, leading to an ICE.  Add the missing reservation.
    
    2025-09-22  Peter Bergner  <bergner@tenstorrent.com>
    
    gcc/
            PR target/121982
            * config/riscv/tt-ascalon-d8.md (tt_ascalon_d8_vec_idiv_byte): New
            define_insn_reservation.
    
    gcc/testsuite/
            PR target/121982
            * gcc.target/riscv/pr121982.c: New test.
    
    Signed-off-by: Peter Bergner <bergner@tenstorrent.com>
    (cherry picked from commit 4275518a06333109b6423c4eb15dd86a6479cef5)

Diff:
---
 gcc/config/riscv/tt-ascalon-d8.md         |  6 ++++++
 gcc/testsuite/gcc.target/riscv/pr121982.c | 16 ++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/gcc/config/riscv/tt-ascalon-d8.md b/gcc/config/riscv/tt-ascalon-d8.md
index 25b99b6129ee..e72012e2b5ba 100644
--- a/gcc/config/riscv/tt-ascalon-d8.md
+++ b/gcc/config/riscv/tt-ascalon-d8.md
@@ -282,6 +282,12 @@
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 ;; Vector integer division
+(define_insn_reservation "tt_ascalon_d8_vec_idiv_byte" 16
+  (and (eq_attr "tune" "tt_ascalon_d8")
+       (eq_attr "type" "vidiv")
+       (eq_attr "sew" "8"))
+  "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
+
 (define_insn_reservation "tt_ascalon_d8_vec_idiv_half" 16
   (and (eq_attr "tune" "tt_ascalon_d8")
        (eq_attr "type" "vidiv")
diff --git a/gcc/testsuite/gcc.target/riscv/pr121982.c b/gcc/testsuite/gcc.target/riscv/pr121982.c
new file mode 100644
index 000000000000..fb9baf886fda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr121982.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-mcpu=tt-ascalon-d8 -mtune=tt-ascalon-d8" } */
+
+/* Verify we don't ICE on the following test cases.  */
+
+typedef char __attribute__((__vector_size__ (32))) vqi;
+typedef short __attribute__((__vector_size__ (32))) vhi;
+typedef int __attribute__((__vector_size__ (32))) vsi;
+typedef long __attribute__((__vector_size__ (32))) vdi;
+
+#define TEST(type) type foo_ ## type (type x, type y) { return x / y; }
+
+TEST(vqi)
+TEST(vhi)
+TEST(vsi)
+TEST(vdi)