[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR target/119275][RISC-V] Avoid calling gen_lowpart in cases where it would ICE

[Jeff Law]

https://gcc.gnu.org/g:18c09a8f601380ebd3b5e51ddc09ffcd85609950

commit 18c09a8f601380ebd3b5e51ddc09ffcd85609950
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Thu Aug 14 14:15:40 2025 -0600

    [PR target/119275][RISC-V] Avoid calling gen_lowpart in cases where it would ICE
    
    So this is a minor bug in the riscv move expanders.  It has a special cases for
    extraction from vector objects which makes assumptions that it can use
    gen_lowpart unconditionally.  That's not always the case.
    
    We can just bypass that special code for cases where we can't use gen_lowpart
    and let the more generic code run. If gen_lowpart_common indicates we've got a
    case that can't be handled we just bypass the special extraction code.
    
    Tested on riscv64-elf and riscv32-elf.  Waiting for pre-commit CI to do its
    thing.
    
            PR target/119275
    gcc/
            * config/riscv/riscv.cc (riscv_legitimize_move): Avoid calling
            gen_lowpart for cases where it'll fail.  Just use standard expander
            paths for those cases.
    
    gcc/testsuite/
            * gcc.target/riscv/pr119275.c: New test.
    
    (cherry picked from commit 44cd33881ff45ee7acc0ae1ddf154163d1eef924)

Diff:
---
 gcc/config/riscv/riscv.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fa7e3ac6a189..25686af4c984 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3686,8 +3686,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 	 not enabled.  In that case we just want to let the standard
 	 expansion path run.  */
       if (riscv_vector::get_vector_mode (smode, nunits).exists (&vmode)
-	  && convert_optab_handler (vec_extract_optab, vmode, smode)
-	  && gen_lowpart_common (vmode, SUBREG_REG (src)))
+	  && gen_lowpart_common (vmode, SUBREG_REG (src))
+	  && convert_optab_handler (vec_extract_optab, vmode, smode))
 	{
 	  rtx v = gen_lowpart (vmode, SUBREG_REG (src));
 	  rtx int_reg = dest;