[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vdiv.vx combine

[Jeff Law]

https://gcc.gnu.org/g:ffb3cf1797bb454c289c5f98f8d3835524511106

commit ffb3cf1797bb454c289c5f98f8d3835524511106
Author: Pan Li <pan2.li@intel.com>
Date:   Mon Jun 2 21:21:18 2025 +0800

    RISC-V: Reconcile the existing test for vdiv.vx combine
    
    Some existing vdiv related test need some adjust for the
    asm check.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adjust
            the asm check for vdiv.
            * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    (cherry picked from commit 4c2d94aed41778226ae08c718459eed5ee65d455)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c        | 8 ++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c        | 8 ++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c   | 4 ++--
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
index 0750d8efc3af..4685ed22a784 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
@@ -3,13 +3,13 @@
 
 #include "vdiv-template.h"
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */
-/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */
 
-/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index 31b228459dc1..59c48d2d9bae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -3,8 +3,8 @@
 
 #include "vdiv-template.h"
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */
-/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
index 6015af9fa405..b574dc42182c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
@@ -3,13 +3,13 @@
 
 #include "vdiv-template.h"
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */
-/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */
 
-/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index ccaa2f899a17..9b46c6be0efb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -3,8 +3,8 @@
 
 #include "vdiv-template.h"
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */
-/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
 /* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */