[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

[Jeff Law]

https://gcc.gnu.org/g:71340d7756fd86179cfabbe1bf2e53ce1e9d7c22

commit 71340d7756fd86179cfabbe1bf2e53ce1e9d7c22
Author: Siarhei Volkau <lis8215@gmail.com>
Date:   Thu May 22 08:52:17 2025 -0600

    [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32
    
    Patch is originally from Siarhei Volkau <lis8215@gmail.com>.
    
    RISC-V has a zero register (x0) which we can use to store zero into memory
    without loading the constant into a distinct register. Adjust the constraints
    of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into
    memory using x0 as the source register.
    
    This patch only affects RISC-V. It has been regression tested on riscv64-elf.
    Jeff has also tested this in his tester (riscv64-elf and riscv32-elf) with no
    regressions.
    
            PR target/70557
    gcc/
            * config/riscv/riscv.md (movdi_32bit): Add "J" constraint to allow storing 0
            directly to memory.
    
    (cherry picked from commit c77085970ec98916e12e079a5a9d9530b86aae71)

Diff:
---
 gcc/config/riscv/riscv.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 5bb13a654d12..ab4b6f943df4 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2534,8 +2534,8 @@
 })
 
 (define_insn "*movdi_32bit"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,  *f,*f,*r,*f,*m,r")
-	(match_operand:DI 1 "move_operand"         " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,  *f,*f,*r,*f,*m,r")
+	(match_operand:DI 1 "move_operand"         " r,i,m,rJ,*J*r,*m,*f,*f,*f,vp"))]
   "!TARGET_64BIT
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"