[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
Jeff Law
law@gcc.gnu.org
Fri Jan 30 06:36:31 GMT 2026
https://gcc.gnu.org/g:38d9543602c3acba7276954c306edd487a1528bc
commit 38d9543602c3acba7276954c306edd487a1528bc
Author: Jeff Law <jlaw@ventanamicro.com>
Date: Thu May 15 09:03:13 2025 -0600
[RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
Thead has the XTHEADBB extension which has a lot of overlap with Zbb. I made
the incorrect assumption that XTHEADBS would largely be like Zbs when
generalizing Shreya's work.
As a result we can't use the operation synthesis code for IOR/XOR because we
don't have binv/bset like capabilities. I should have double checked on
XTHEADBS, my bad.
Anyway, the fix is trivial. Don't allow bset/binv based on XTHEADBS.
Already spun in my tester. Spinning in the pre-commit CI system now.
PR target/120223
gcc/
* config/riscv/riscv.cc (synthesize_ior_xor): XTHEADBS does not have
single bit manipulations.
gcc/testsuite/
* gcc.target/riscv/pr120223.c: New test.
(cherry picked from commit 87d0daab1ec9d5c901295e8045cbd67f80b2fa23)
Diff:
---
gcc/config/riscv/riscv.cc | 4 ++--
gcc/testsuite/gcc.target/riscv/pr120223.c | 4 ++++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 295c582072eb..80a725020b1f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -14245,7 +14245,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
{
/* Trivial cases that don't need synthesis. */
if (SMALL_OPERAND (INTVAL (operands[2]))
- || ((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZBKB)
+ || ((TARGET_ZBS || TARGET_ZBKB)
&& single_bit_mask_operand (operands[2], word_mode)))
return false;
@@ -14282,7 +14282,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
/* If we're flipping all but a small number of bits we can pre-flip
the outliers, then flip all the bits, which would restore those
bits that were pre-flipped. */
- if ((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZBKB)
+ if ((TARGET_ZBS || TARGET_ZBKB)
&& budget < 0
&& code == XOR
&& popcount_hwi (~INTVAL (operands[2])) < original_budget)
diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c
new file mode 100644
index 000000000000..fae21b6d1ece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120223.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=thead-c906" } */
+long foo(long x) { return x ^ 0x80000000; }
+
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