[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fix various RISC-V testsuite regressions after volatile patch

[Jeff Law]

https://gcc.gnu.org/g:321ac9d3c1962732634c84da1b70d63a75641fca

commit 321ac9d3c1962732634c84da1b70d63a75641fca
Author: Jeff Law <jeffrey.law@oss.qualcomm.com>
Date:   Wed Dec 17 09:08:09 2025 -0700

    Fix various RISC-V testsuite regressions after volatile patch
    
    The RISC-V port showed a handful of regressions after integrating the final
    patch from HJ for volatile accesses.
    
    The core issue is the RISC-V port has two patterns which are basically the same
    RTL form with the exception of a clobber of a scratch operand.
    
    Those patterns do differ materially in their condition in that one is more
    strict than the other.  The pattern with the stricter condition also happens to
    be the one without the clobber.  So it's clearly stricter across both of those
    axis.
    
    The stricter pattern naturally generates more efficient (loopless) code for the
    relevant atomic operations.  We have a handful of tests in the RISC-V port
    which verify that we use the right sequences.
    
    With HJ's patch the insn gets re-matched during combine which adds the clobber
    and ultimately matches the more general pattern (which is currently first in
    the MD file).  So we end up with the less efficient sequence and the relevant
    tests naturally fail.
    
    This patch just puts the two patterns in the right order with the stricter
    pattern coming first.  I also walked through the rest of the sync.md patterns
    and none obviously had the same problem.
    
    This has been bootstrapped and regression tested on risc-v with both the
    Pioneer and BPI F3 systems.
    
    I'll let pre-commit CI chew on it overnight before the planned commit tomorrow.
    
    jeff
    
    gcc/
            * config/riscv/sync.md (atomic compare and set): Reorder patterns
            so the stricter pattern comes first.
    
    (cherry picked from commit 09ed6a3d8df7a333651b3ba19e780eb6fa329cf5)

Diff:
---
 gcc/config/riscv/sync.md | 54 ++++++++++++++++++++++++------------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 01eab1a1ef36..bc8a562b1cda 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -528,33 +528,6 @@
 
 ; Atomic CAS ops
 
-(define_insn "zalrsc_atomic_cas_value_strong<mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=&r")
-	(match_operand:GPR 1 "memory_operand" "+A"))
-   (set (match_dup 1)
-	(unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ")
-			      (match_operand:GPR 3 "reg_or_0_operand" "rJ")
-			      (match_operand:SI 4 "const_int_operand")  ;; mod_s
-			      (match_operand:SI 5 "const_int_operand")] ;; mod_f
-	 UNSPEC_COMPARE_AND_SWAP))
-   (clobber (match_scratch:GPR 6 "=&r"))]
-  "TARGET_ZALRSC"
-  {
-    enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
-    enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
-    /* Find the union of the two memory models so we can satisfy both success
-       and failure memory models.  */
-    operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure));
-    return "1:\;"
-	   "lr.<amo>%I5\t%0,%1\;"
-	   "bne\t%0,%z2,1f\;"
-	   "sc.<amo>%J5\t%6,%z3,%1\;"
-	   "bnez\t%6,1b\;"
-	   "1:";
-  }
-  [(set_attr "type" "multi")
-   (set (attr "length") (const_int 16))])
-
 ;; Implement compare_exchange with a conservative leading fence when
 ;; model_failure is seq_cst.
 ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7
@@ -588,6 +561,33 @@
 	(symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[5]))) ? 8
 		      : 4)"))])
 
+(define_insn "zalrsc_atomic_cas_value_strong<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=&r")
+	(match_operand:GPR 1 "memory_operand" "+A"))
+   (set (match_dup 1)
+	(unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ")
+			      (match_operand:GPR 3 "reg_or_0_operand" "rJ")
+			      (match_operand:SI 4 "const_int_operand")  ;; mod_s
+			      (match_operand:SI 5 "const_int_operand")] ;; mod_f
+	 UNSPEC_COMPARE_AND_SWAP))
+   (clobber (match_scratch:GPR 6 "=&r"))]
+  "TARGET_ZALRSC"
+  {
+    enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
+    enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
+    /* Find the union of the two memory models so we can satisfy both success
+       and failure memory models.  */
+    operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure));
+    return "1:\;"
+	   "lr.<amo>%I5\t%0,%1\;"
+	   "bne\t%0,%z2,1f\;"
+	   "sc.<amo>%J5\t%6,%z3,%1\;"
+	   "bnez\t%6,1b\;"
+	   "1:";
+  }
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 16))])
+
 (define_expand "atomic_compare_and_swap<mode>"
   [(match_operand:SI 0 "register_operand" "")   ;; bool output
    (match_operand:GPR 1 "register_operand" "")  ;; val output