[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmseq.vv combine case 1 with GR2VR cost 0, 1 and 15
Jeff Law
law@gcc.gnu.org
Sat Jan 17 07:22:29 GMT 2026
https://gcc.gnu.org/g:6b0cf051b7a0d5618154da4ea1d2f26d2c4f9b37
commit 6b0cf051b7a0d5618154da4ea1d2f26d2c4f9b37
Author: Pan Li <pan2.li@intel.com>
Date: Mon Nov 10 09:08:13 2025 +0800
RISC-V: Add test for vec_duplicate + vmseq.vv combine case 1 with GR2VR cost 0, 1 and 15
Add asm dump check and run test for vec_duplicate + vmseq.vv
combine to vmseq.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
for vmseq.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
(cherry picked from commit d8b523e1d0ae33c0fcc9e1e2f0513035630d9358)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 1 +
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c | 15 +++
.../riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c | 15 +++
.../riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c | 15 +++
.../riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c | 15 +++
18 files changed, 209 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 1a48afa2788f..d9cbe02d5fa9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 2b00614d2f4c..6c14e94a6bcc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 8cbf47e2eb41..c1d72169e25a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vwaddu.wx} 1 } } */
/* { dg-final { scan-assembler-times {vwsubu.wx} 1 } } */
/* { dg-final { scan-assembler-times {vwmaccu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index b659f7fbc068..87af77b33d4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 9aa9029d3d03..163bfc3b3fde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 2ffd850fa9f0..a04516e9bd05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 8bb5c50413ae..85962bf30139 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 957fcde118fa..211def9f8e9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 9f5351615dda..9f3619670259 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 069efefa7fa7..426d910e778f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 04332ff70b57..755873007b67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -36,3 +36,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 9deb635d0b9c..e8478495d2cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 194f304c4293..950803e31dd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -421,6 +421,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \
DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \
DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \
+ DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq) \
DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \
DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \
DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index aace7ca8457d..284992bb132c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -6022,4 +6022,140 @@ int64_t TEST_BINARY_DATA(int64_t, merge)[][3][N] =
},
};
+uint8_t TEST_BINARY_DATA(uint8_t, eq)[][3][N] =
+{
+ {
+ { 127 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 127, 127, 127, 127,
+ 128, 128, 128, 128,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 255 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 255, 255, 255, 255,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ },
+ },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, eq)[][3][N] =
+{
+ {
+ { 32767 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 32767, 32767, 32767, 32767,
+ 32768, 32768, 32768, 32768,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 65535 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 65535, 65535, 65535, 65535,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ },
+ },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, eq)[][3][N] =
+{
+ {
+ { 2147483647 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483648, 2147483648, 2147483648, 2147483648,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 4294967295 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ },
+ },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, eq)[][3][N] =
+{
+ {
+ { 9223372036854775807ull },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
+ 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 18446744073709551615ull },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ },
+ },
+};
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c
new file mode 100644
index 000000000000..12046c398019
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint16_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c
new file mode 100644
index 000000000000..7d2be3007466
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint32_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c
new file mode 100644
index 000000000000..7a6f664ca436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint64_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c
new file mode 100644
index 000000000000..619e3d5fc378
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint8_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
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