[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests

[Jeff Law]

https://gcc.gnu.org/g:83f7bd9f5583e32a7567e099e0f2a0e76cb2db12

commit 83f7bd9f5583e32a7567e099e0f2a0e76cb2db12
Author: Paul-Antoine Arras <parras@baylibre.com>
Date:   Wed Jul 9 08:36:24 2025 -0600

    [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests
    
    zvfh is not enabled at the testsuite level. It has to be enabled on a testcase
    by testcase basis. This was correctly done for compile tests but not for run
    tests. This patch fixes it.
    Also, to ensure correct results with half-precision floats, MAX_RELATIVE_DIFF is
    set according to the type.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h: Set
            MAX_RELATIVE_DIFF depending on type.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: Enable zvfh.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: Likewise.
    
    (cherry picked from commit f32d34c2b03c55c3ae7cf282e5d2cc24a4d758e4)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h    | 7 ++++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c      | 2 +-
 9 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h
index 3dc39993e74e..3dadfabfeaff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h
@@ -6,6 +6,10 @@
 #define TYPE_FABS(x, T)                                                        \
   (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x))
 
+#define MAX_RELATIVE_DIFF(T)                                                   \
+  (__builtin_types_compatible_p (T, _Float16) ? 0.1f  :                        \
+  (__builtin_types_compatible_p (T, float)    ? 0.01f : 0.01))
+
 int
 main ()
 {
@@ -23,7 +27,8 @@ main ()
       for (k = 0; k < N; k++)
 	{
 	  T diff = expect[k] - TEST_OUT[k];
-	  if (TYPE_FABS (diff, T) > .01 * TYPE_FABS (expect[k], T))
+	  if (TYPE_FABS (diff, T)
+	      > MAX_RELATIVE_DIFF (T) * TYPE_FABS (expect[k], T))
 	    __builtin_abort ();
 	}
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
index 5bb926daf1a7..982dd9736acc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
index be4dc1dadd2d..400bbcd1d79f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
index 812e6088ac28..21c1860c0f1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
index 48c288001a18..163b5bd21b42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
index b960e7aeecb0..71f350f74e22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
index 2be891776186..e252e0dc21a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
index 4f10600ece9c..439fd3e50560 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
index 7bed0ed940c9..b9d66bafeadc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"