[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

[Jeff Law]

https://gcc.gnu.org/g:3426d7dbdc7a821f35f2428afa67710c0a44875a

commit 3426d7dbdc7a821f35f2428afa67710c0a44875a
Author: Dimitar Dimitrov <dimitar@dinux.eu>
Date:   Fri Jun 20 20:57:15 2025 +0300

    RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs
    
    Some test cases explicitly set -march or -mcpu with extensions which
    are not compatible with the E ABI variants.  This leads to spurious
    errors when toolchain has been configured for RV32E base ISA and
    ILP32E ABI:
      cc1: error: ILP32E ABI does not support the 'D' extension
    
    Also, test gcc.target/riscv/rvv/base/pr119164.c implicitly requires
    rv64 since it explicitly selects -march=rv64gcv_zvl256b:
      cc1: error: ABI requires '-march=rv32'
    
    Testing done:
     - Ensured cross riscv64-unknown-linux-gnu has no difference in test
       output with and without the patch.
     - For riscv32-unknown-elf  there are no new failures. Test case pr119164.c
       no longer fails and is now marked as unsupported.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/mcpu-xt-c908.c: Disable for E ABI variants.
            * gcc.target/riscv/mcpu-xt-c908v.c: Ditto.
            * gcc.target/riscv/mcpu-xt-c910.c: Ditto.
            * gcc.target/riscv/mcpu-xt-c910v2.c: Ditto.
            * gcc.target/riscv/mcpu-xt-c920.c: Ditto.
            * gcc.target/riscv/mcpu-xt-c920v2.c: Ditto.
            * gcc.target/riscv/pr118241.c: Ditto.
            * gcc.target/riscv/pr120223.c: Ditto.
            * gcc.target/riscv/rvv/base/pr119164.c: Disable for E ABI variants
            and for 32-bit ISA.
    
    Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
    (cherry picked from commit 81d738275f45e497c0c90ce75d407354fca7d891)

Diff:
---
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c     | 2 +-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c    | 2 +-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c    | 2 +-
 gcc/testsuite/gcc.target/riscv/pr118241.c          | 2 +-
 gcc/testsuite/gcc.target/riscv/pr120223.c          | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
index cb28baf1ce72..4ad82a81dec8 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */
 /* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
index 1b1ee188229f..bb9e3109920a 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */
 /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
index 1e276659c3ea..397e7b192670 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
 /* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
index 6a54f0988780..9e39c9f89eb4 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */
 /* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
index 6bcd687e7424..4cce90a1e945 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */
 /* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
index 36a6267849bf..1f21d07f37ad 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */
 /* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */
diff --git a/gcc/testsuite/gcc.target/riscv/pr118241.c b/gcc/testsuite/gcc.target/riscv/pr118241.c
index f1dc44bce0ca..768ea050f1aa 100644
--- a/gcc/testsuite/gcc.target/riscv/pr118241.c
+++ b/gcc/testsuite/gcc.target/riscv/pr118241.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-options "-march=rv64gc_zicbop" { target { rv64 } } } */
 /* { dg-options "-march=rv32gc_zicbop" { target { rv32 } } } */
 /* { dg-skip-if "" { *-*-* } { "-O0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c
index fae21b6d1ece..d6afd866c585 100644
--- a/gcc/testsuite/gcc.target/riscv/pr120223.c
+++ b/gcc/testsuite/gcc.target/riscv/pr120223.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-options "-mcpu=thead-c906" }  */
 long foo(long x) { return x ^ 0x80000000; }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
index a39a7f177f05..266e9485880c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
@@ -1,7 +1,7 @@
 /* Reduced from SPEC2017 blender: node_texture_util.c.
    The conditional function call was tripping mode switching state machine */
 
-/* { dg-do compile } */
+/* { dg-do compile  { target { rv64 && { ! riscv_abi_e } } } } */
 /* { dg-options " -Ofast -march=rv64gcv_zvl256b -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 void *a;