[gcc r16-6785] RISC-V: Enable the ZD constraint only when xmipscbop is enabled [PR123092]

[Peter Bergner]

https://gcc.gnu.org/g:58977d739238d927c02f64c6417c887df86a5f55

commit r16-6785-g58977d739238d927c02f64c6417c887df86a5f55
Author: Peter Bergner <bergner@tenstorrent.com>
Date:   Wed Jan 14 15:12:21 2026 -0600

    RISC-V: Enable the ZD constraint only when xmipscbop is enabled [PR123092]
    
    The ZD constraint is specific to the mips prefetch instruction.  It is
    currently always enabled, leading to ICEs when xmipscbop is disabled.
    Solved by only enabling the ZD constraint whenever xmipscbop is enabled.
    
    2026-01-14  Peter Bergner  <bergner@tenstorrent.com>
    
    gcc/
            PR target/123092
            * config/riscv/constraints.md (ZD): Disable when xmipscbop is disabled.
    
    Signed-off-by: Peter Bergner <bergner@tenstorrent.com>

Diff:
---
 gcc/config/riscv/constraints.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 85b4fdce5ee0..673b05954e12 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -333,7 +333,7 @@
 
 (define_address_constraint "ZD"
   "An address operand that is valid for a mips prefetch instruction"
-  (match_test "riscv_prefetch_offset_address_p (op, mode)"))
+  (match_test "TARGET_XMIPSCBOP && riscv_prefetch_offset_address_p (op, mode)"))
 
 (define_constraint "Ou07"
   "A 7-bit unsigned immediate."