[gcc(refs/users/meissner/heads/work233-float)] Add BF/HF neg, abs operands and logical insns.

[Michael Meissner]

https://gcc.gnu.org/g:16702c5871745c53b5c0d9d10e6717bb2308d553

commit 16702c5871745c53b5c0d9d10e6717bb2308d553
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Jan 6 15:09:41 2026 -0500

    Add BF/HF neg, abs operands and logical insns.
    
    2026-01-06  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/float16.md (abs<mode>2): Fix absolute value to generate
            xxlandc.
            (boolc<mode>3): Delete second boolc, which is incorrect.

Diff:
---
 gcc/config/rs6000/float16.md | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md
index ab257da20ccc..7a24236279e0 100644
--- a/gcc/config/rs6000/float16.md
+++ b/gcc/config/rs6000/float16.md
@@ -576,8 +576,9 @@
   [(set (match_dup 2)
 	(match_dup 3))
    (set (match_dup 0)
-	(and:FP16 (match_dup 1)
-		  (not:FP16 (match_dup 2))))]
+	(and:FP16 (not:FP16 (match_dup 2))
+		  (match_dup 1)))]
+		  
 {
   if (GET_CODE (operands[2]) == SCRATCH)
     operands[2] = gen_reg_rtx (<MODE>mode);
@@ -722,17 +723,6 @@
    %q3 %0,%1,%2"
   [(set_attr "type" "veclogical,logical")])
 
-(define_insn "*boolc<mode>3"
-  [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r")
-	(match_operator:FP16 3 "boolean_operator"
-	 [(match_operand:FP16 1 "gpc_reg_operand" "wa,r")
-	  (not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r"))]))]
-  "TARGET_FLOAT16"
-  "@
-   xxl%q3 %x0,%x1,%x2
-   %q3 %0,%1,%2"
-  [(set_attr "type" "veclogical,logical")])
-
 ;; NOR and NAND insns.
 (define_insn "*boolcc<mode>3"
   [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r")