[gcc(refs/users/meissner/heads/work237-dmf)] Add support for dense math registers.
Michael Meissner
meissner@gcc.gnu.org
Fri Feb 13 05:03:10 GMT 2026
https://gcc.gnu.org/g:202909597927b1bce68aec8542d52c2c118f71fa
commit 202909597927b1bce68aec8542d52c2c118f71fa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Feb 12 23:48:18 2026 -0500
Add support for dense math registers.
This patch adds the -mdense-math option for -mcpu=future. The next set of
patches will support for using dense math registers with the MMA instructions.
gcc/
2026-02-12 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define
__DENSE_MATH__ if we have dense math registers.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Add -mdense-math.
(POWERPC_MASKS): Add comment about adding -mdense-math in a future
patch.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not
allow -mdense-math unless -mcpu=future is used.
(rs6000_opt_masks): Add -mdense-math support.
* config/rs6000/rs6000.opt (-mdense-math): New option.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add -mdense-math.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 4 ++++
gcc/config/rs6000/rs6000-cpus.def | 7 ++++++-
gcc/config/rs6000/rs6000.cc | 10 ++++++++++
gcc/config/rs6000/rs6000.opt | 4 ++++
gcc/doc/invoke.texi | 7 +++++++
5 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index eb6a881aa9bd..a7eb951b014d 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -590,6 +590,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
/* Tell the user if we support the MMA instructions. */
if ((flags & OPTION_MASK_MMA) != 0)
rs6000_define_or_undefine_macro (define_p, "__MMA__");
+ /* Tell the user if we support the dense math registers for use with MMA and
+ cryptography. */
+ if ((flags & OPTION_MASK_DENSE_MATH) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__DENSE_MATH__");
/* Whether pc-relative code is being generated. */
if ((flags & OPTION_MASK_PCREL) != 0)
rs6000_define_or_undefine_macro (define_p, "__PCREL__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index dc67e287672e..a775f1b1b6dd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -88,9 +88,13 @@
During the development of the power10 support for GCC, using load/store
vector pair instructions for string operations was turned off by default,
because there was a use case that had really bad performance. Assume this
- will be fixed in potential future machines. */
+ will be fixed in potential future machines.
+
+ Do not enable -mdense-math by default with -mcpu=future until all of the
+ basic dense math register support is enabled. */
#define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \
| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
+ /* | OPTION_MASK_DENSE_MATH */ \
| OPTION_MASK_FUTURE)
/* Flags that need to be turned off if -mno-vsx. */
@@ -124,6 +128,7 @@
| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
+ | OPTION_MASK_DENSE_MATH \
| OPTION_MASK_DFP \
| OPTION_MASK_DLMZB \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3454a090dbc2..68d5e95179f7 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4410,6 +4410,15 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
+ /* Turn off dense math register support on non-future systems. */
+ if (TARGET_DENSE_MATH && !TARGET_FUTURE)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_DENSE_MATH) != 0)
+ error ("%qs requires %qs", "-mdense-math", "-mcpu=future");
+
+ rs6000_isa_flags &= ~OPTION_MASK_DENSE_MATH;
+ }
+
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -24463,6 +24472,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
false, true },
{ "cmpb", OPTION_MASK_CMPB, false, true },
{ "crypto", OPTION_MASK_CRYPTO, false, true },
+ { "dense-math", OPTION_MASK_DENSE_MATH, false, true },
{ "direct-move", 0, false, true },
{ "dlmzb", OPTION_MASK_DLMZB, false, true },
{ "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 9f3519da77b2..436309bb09c5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -639,6 +639,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mdense_math
+Target Mask(DENSE_MATH) Var(rs6000_isa_flags)
+Generate (do not generate) instructions that use dense math registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b574f85cc3f4..120f76a6f18f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -32674,6 +32674,13 @@ This option is enabled by default.
Enable or disable warnings about deprecated @samp{vector long ...} Altivec
type usage. This option is enabled by default.
+@opindex mdense-math
+@opindex mno-dense-math
+@item -mdense-math
+@itemx -mno-dense-math
+Generate (do not generate) code that uses the dense math registers.
+This option is enabled by default.
+
@end table
@node RX Options
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