[gcc(refs/users/meissner/heads/work041)] Rework 0.0 handling in XXSPLTIDP.

[Michael Meissner]

https://gcc.gnu.org/g:b294814733b9edc69461605d4b5a0ea150c0f735

commit b294814733b9edc69461605d4b5a0ea150c0f735
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 18 16:05:16 2021 -0400

    Rework 0.0 handling in XXSPLTIDP.
    
    gcc/
    2021-03-18  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/altivec.md (xxspltidp_v2df): Delete special
            handling of 0.0.  Add comment about the denormal.

Diff:
---
 gcc/config/rs6000/rs6000.md | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 83b1edc65ac..79375bffc9e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7529,20 +7529,16 @@
   DONE;
 })
 
-;; Load a SFmode/DFmode constant via the ISA 3.1 XXSPLTIDP instruction
+;; Convert a load of a SFmode/DFmode constant to use the ISA 3.1 XXSPLTIDP
+;; instruction if we can.  We don't do this for 0.0 to allow the move patterns
+;; to generate the smaller XXSPLTIB/VSPLTISW/XXLXOR to zero the register.
 (define_split
   [(set (match_operand:SFDF 0 "vsx_register_operand")
 	(match_operand:SFDF 1 "xxspltidp_operand"))]
-  "TARGET_POWER10 && TARGET_VSX"
+  "TARGET_POWER10 && TARGET_VSX && operands[1] != CONST0_RTX (<MODE>mode)"
   [(set (match_dup 0)
 	(unspec:SFDF [(match_dup 2)] UNSPEC_XXSPLTIDP))]
 {
-  if (operands[1] == CONST0_RTX (<MODE>mode))
-    {
-      emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
-      DONE;
-    }
-
   long value;
   const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (operands[1]);
   REAL_VALUE_TO_TARGET_SINGLE (*rv, value);