[gcc(refs/vendors/AWS/heads/Arm64/gcc-7-branch)] aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]

[Sebastian Pop]

https://gcc.gnu.org/g:37c58b17785af416b1d78ddd40ec3b1d394a584c

commit 37c58b17785af416b1d78ddd40ec3b1d394a584c
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Apr 2 12:57:11 2020 +0200

    aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]
    
    The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits
    invalid RTL.
    For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits
    into that mode) and x being SImode; for non-CONST_INT y it zero extends y
    into SImode and compares that against x, for CONST_INT y it zero extends y
    into SImode.  The problem is that when the zero extended constant isn't
    usable directly, it forces it into a REG, but with y_mode mode, and then
    compares against y.  That is wrong, because it should force it into a SImode
    REG and compare that way.
    
    2020-04-02  Jakub Jelinek  <jakub@redhat.com>
    
    gcc/
            PR target/94435
            * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
            y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
    
    gcc/testsuite/
            * gcc.target/aarch64/pr94435.c: New test.
    
    (cherry picked from commit df562b12d90699c20923f91df48eed08ebcb572e)

Diff:
---
 gcc/config/aarch64/aarch64.c               |  5 ++++-
 gcc/testsuite/gcc.target/aarch64/pr94435.c | 25 +++++++++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5ccb13b46fe..a0685a5ad41 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1230,7 +1230,10 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y,
   if (y_mode == QImode || y_mode == HImode)
     {
       if (CONST_INT_P (y))
-	y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
+	{
+	  y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
+	  y_mode = SImode;
+	}
       else
 	{
 	  rtx t, cc_reg;
diff --git a/gcc/testsuite/gcc.target/aarch64/pr94435.c b/gcc/testsuite/gcc.target/aarch64/pr94435.c
new file mode 100644
index 00000000000..5713c14d5f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr94435.c
@@ -0,0 +1,25 @@
+/* PR target/94435 */
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+	{
+	  __atomic_load_n (&e, 0);
+	  if (foo (2))
+	    __sync_val_compare_and_swap (&c, 0, f);
+	  b = 1;
+	  if (h == e)
+	    break;
+	}
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}