[Bug rtl-optimization/123267] [16 Regression] ICE building libstdc++-v3/src/c++20/tzdb.cc

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123267

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Sergei Trofimovich from comment #3)
> For me bisect landed on r16-6333-gac64ceb33bf05b "ifcvt: cond zero arith:
> handle subreg for shift count".

That is what I expected to be one of the ifcvt patches.

Also I am reducing this. Should be done in an hour or 2.