[Bug rtl-optimization/123267] [16 Regression] ICE building libstdc++-v3/src/c++20/tzdb.cc

[slyfox at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123267

--- Comment #3 from Sergei Trofimovich <slyfox at gcc dot gnu.org> ---
For me bisect landed on r16-6333-gac64ceb33bf05b "ifcvt: cond zero arith:
handle subreg for shift count".