[Bug target/116149] RISC-V: Miscompile at -O3 with zvl256b -mrvv-vector-bits=zvl

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116149

--- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> ---
It looks like the problem is a wrong mode_idx attribute for the wx variants of
the adds.  The widening adds's mode is the one of the non-widened input operand
but for the wx/scalar variants this is a scalar mode instead of a vector mode.
That confuses avlprop so that it uses 1 instead of 4 as vector length.

Testing a patch.