[Bug target/116149] RISC-V: Miscompile at -O3 with zvl256b -mrvv-vector-bits=zvl

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116149

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
> Still present when rvv_ta_all_1s=true is omitted.

My result is '0' when rvv_ta_all_1s=false, is that what you meant?

I didn't have time to check this in detail but it's not the missing else for
masked loads.  It looks like we should use the "tu" policy instead of "ta" when
doing those intermediate steps.  When I change everything with a vl != 4 (so 3
and 1) to the "tu" policy the result is correct.  Need to check where we go
wrong.