[Bug target/104039] AArch64 Redundant instruction moving general to vector register

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104039

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to fail|                            |9.1.0
           Severity|enhancement                 |normal
   Target Milestone|---                         |9.5
      Known to work|                            |8.5.0

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
So back in GCC 8.5 we used dup to create the initial vector and then did an
insert. for floating point registers this works fine.
But if we do:
typedef double  f64x2 __attribute__((vector_size(16)));

f64x2 combine(double a, double b) {
    asm("// %0 %1":"+r"(a));
        f64x2 v = {a,b};
    return v;
}

We get two ins which we should not get.
While in GCC 8.5.0 we got:
        fmov    x0, d0
// x0 x0
        fmov    d0, x0
        dup     v0.2d, v0.d[0]
        ins     v0.d[1], v1.d[0]

Which is also wrong because there is no reason for a fmov/dup, just fmov is
enough.