[Bug target/104039] AArch64 Redundant instruction moving general to vector register
pinskia at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Sat Jan 15 03:40:30 GMT 2022
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104039
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Severity|normal |enhancement
Last reconfirmed| |2022-01-15
Ever confirmed|0 |1
Target| |aarch64
Keywords| |ra
Status|UNCONFIRMED |NEW
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.
The problem is the register allocator.
It goes from:
(insn 18 10 19 2 (set (reg:DI 99)
(reg:DI 0 x0 [ a ])) "/app/example.cpp":4:49 53 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 0 x0 [ a ])
(nil)))
(insn 19 18 8 2 (set (reg:DI 100)
(reg:DI 1 x1 [ b ])) "/app/example.cpp":4:49 53 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 1 x1 [ b ])
(nil)))
(insn 8 19 15 2 (set (reg:V2DI 95 [ a ])
(subreg:V2DI (reg:DI 99) 0)) "/app/example.cpp":5:16 1206
{*aarch64_simd_movv2di}
(expr_list:REG_DEAD (reg:DI 99)
(nil)))
To:
(insn 8 10 15 2 (set (reg:V2DI 32 v0 [orig:95 a ] [95])
(reg:V2DI 0 x0 [99])) "/app/example.cpp":5:16 1206
{*aarch64_simd_movv2di}
(nil))
And then that gets split into:
(insn 22 10 23 2 (set (reg:V2DI 32 v0 [orig:95 a ] [95])
(vec_concat:V2DI (reg:DI 0 x0 [99])
(const_int 0 [0]))) "/app/example.cpp":5:16 1919
{move_lo_quad_internal_v2di}
(nil))
(insn 23 22 15 2 (set (reg:V2DI 32 v0 [orig:95 a ] [95])
(vec_concat:V2DI (vec_select:DI (reg:V2DI 32 v0 [orig:95 a ] [95])
(parallel:V2DI [
(const_int 0 [0])
]))
(reg:DI 1 x1 [+8 ]))) "/app/example.cpp":5:16 1932
{aarch64_simd_move_hi_quad_v2di}
(nil))
Maybe we should have done the expansion to use an fmov in the first place via a
special pattern which then gets expanded correctly might be better, I don't
know.
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