[Bug rtl-optimization/59461] missed zero-extension elimination in the combiner

[ebotcazou at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59461

--- Comment #9 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> This is a notoriously hard topic to address. All instructions affect the
> full 64-bit register including those that do 32-bit arithmetic i.e. they
> will set/clear the upper bits to replicate bit-31.

So there are different 32-bit and 64-bit 'add' instructions for example?  That
might nevertheless be OK for WORD_REGISTER_OPERATIONS.

> In terms of instruction definition we therefore have instructions that
> operate on DImode and instructions that operate on SImode. The SImode
> instructions just don't need to worry about what is happening with the upper
> bits.

Likewise for SPARC, which is WORD_REGISTER_OPERATIONS too, but doesn't care
about the upper bits in 32-bit mode and has a single 'add' instruction (but
maintains 32-bit _and_ 64-bit condition codes for every instruction).

> I don't know if any of that subtlety affects this yet.

Bugs in the nonzero_bits machinery are not to be ruled out either.  I'm willing
to help of course but I don't have access to MIPS64 hardware.