[Bug rtl-optimization/59461] missed zero-extension elimination in the combiner

[matthew.fortune at imgtec dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59461

--- Comment #8 from Matthew Fortune <matthew.fortune at imgtec dot com> ---
(In reply to Eric Botcazou from comment #7)
> > I'm yet to get my head around what the issue is but if anyone has a pointer
> > based on the potential impact on MIPS64 as described above then I'd be
> > grateful.
> 
> Is WORD_REGISTER_OPERATIONS correct for MIPS64, i.e. do all instructions
> operate on the full 64-bit integer registers?

This is a notoriously hard topic to address. All instructions affect the full
64-bit register including those that do 32-bit arithmetic i.e. they will
set/clear the upper bits to replicate bit-31. However, according to the
architecture they logically operate on 32-bits and require that all inputs are
canonical (sign bit replicated) otherwise the operation is invalid. So it would
not matter whether the register was 33 bits or 1000 bits wide as long as all
bits from 32 upwards replicate bit-31. The upper bits only become relevant once
a 32-bit value is cast to a 64-bit value where sign extension is free and zero
extension is an operation. truncation from 64-bit to 32-bit is a sign extension
from bit-31 regardless of whether it is truncating to signed or unsigned.

In terms of instruction definition we therefore have instructions that operate
on DImode and instructions that operate on SImode. The SImode instructions just
don't need to worry about what is happening with the upper bits.

I don't know if any of that subtlety affects this yet.