[Bug target/70220] [x86] interrupt attribute optionally needs to provide read, write and control the set of saved registers

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70220

--- Comment #3 from H.J. Lu <hjl.tools at gmail dot com> ---
(In reply to Wink Saville from comment #2)
> (In reply to H.J. Lu from comment #1)
> > (In reply to Wink Saville from comment #0)
> > > I have identified one possible problem and with this scheme, what if the
> > > compiler needs to setup a stack frame by pushing rbp and then moving rsp to
> > > rbp, how would that case be handled.
> > 
> > Why should be it a problem unless you don't want to restore RSP and RBP
> > to its original values upon returning from ISR.  Please provide an example
> > here.
> 
> Here a possible example, I added a printf and local variables to
> timer_reschedule_isr:
> 
> void timer_reschedule_isr(struct intr_frame* frame) {
>   __asm__ volatile(""::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp",
>                          "r8",  "r9",  "r10", "r11", "r12", "r13", "r14",
> "r15");
> 

> If I now remove "rbp" from the clobber list it compiles:
>

rbp is special.  Will remove rbp from the clobber list cause any
problems here?