[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

--- Comment #3 from ktkachov at gcc dot gnu.org ---
(In reply to Richard Earnshaw from comment #1)
> Confirmed based on inspection.
> 
> The patch suggested is not correct, since vcvtr can be conditional and it
> shares the same basic pattern.

In the l<vrint_pattern><su_optab><mode>si2 pattern we use the VCVT iterator
which iterates over [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA] all of which
cannot be conditional. 

UNSPEC_VRINTR is handled by the vrint_variant int attribute, but it's not
utilised in this pattern because the VCVT iterator doesn't include
UNSPEC_VRINTR

So I think the proposed patch is correct, but would need to be sent to
gcc-patches with a the testcase properly added to the testsuite.