[Bug target/78255] [5/6/7 regression] Indirect sibling call causing wrong code generation for ARM

[wilco at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78255

--- Comment #7 from wilco at gcc dot gnu.org ---
(In reply to ktkachov from comment #6)
> (In reply to wilco from comment #5)
> > (In reply to avieira from comment #4)
> > > OK so after some extra debugging and digging I found that the postreload
> > > pass is basically turning the direct sibcall into an indirect sibcall. It
> > > takes cost into consideration, but does this only looking at the operands of
> > > the call, i.e. the cost of a symbolref vs the cost of a register. It does
> > > not take into consideration that it is doing a call. This doesn't seem like
> > > a good idea to me.
> > 
> > Also it looks like various other targets may have the same issue as using
> > one instruction for direct and indirect tailcalls is common among RISC
> > targets.
> > 
> > So this is another generic cost issue whether it isn't possible to return
> > correct costs.
> > 
> 
> Regardless of whether the profitability logic is right or not, this is a
> correctness question, so postreload should cancel this transformation
> regardless of costs

The chosen pattern is legal so the transformation is effectively correct. We
could explicitly disallow making changes to calls and tailcalls, but what other
potentially incorrect transformations should we explicitly exclude?