[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |ysrumyan at gmail dot com

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Ilya Enkovich from comment #1)
> For call arguments we usually store bounds passed in bounds tables and then
> fill bounds passed in registers.  But with -fschedule-insns we have order
> changed and all hard registers are filled with values before BNDSTX.  This
> is not a nice schedule because it requires additional spills.  Seems LRA
> fails to spill a register when all of them are used to pass args.  This
> situation didn't happen before because bounds registers is the first case
> when we use all registers to pass args. Should LRA be able to spill/fill
> initialized hard reg? Can it be fixed or we better avoid such scheduling?

There are a bunch of functions in i386.c (please grep for TARGET_SCHED_REORDER,
TARGET_SCHED_ADJUST_PRIORITY and TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK)
that are intended to solve issues like this. AFAICS, they have to be enhanced
to handle bound registers and to preserve the order of insns involving bound
regs.

I'm adding author of these functions to CC.