[Bug target/60138] superh single/double precision fpu mode setting is backwards and unusable

[bugdal at aerifal dot cx]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60138

--- Comment #2 from Rich Felker <bugdal at aerifal dot cx> ---
> No need to move it to TLS, since the FPSCR register is usually already part of
> an execution context (i.e. thread) and will be saved and restored accordingly.

This does not help. The compiler constantly clobbers the FPSCR with the values
read from __fpscr_values[]. If you want to affect a change to the fpu behavior,
you'd have to modify the values in this array, and they are global, not
thread-local, which is wrong.

If use of __fpscr_values is eliminated, of course this will not matter.

Right now this is a blocking issue for musl libc having properly a working sh
port (floating point tests fail because fenv is not honored). We could treat sh
as a no-fenv port, but I'd rather not do that since the hardware does have
working fenv and it's just gcc messing it up; also we don't really support
no-fenv targets in a conforming way (we don't provide errno for math functions)
so I'd much rather have fenv.