[Bug rtl-optimization/55757] Suboptimal interrupt prologue/epilogue for ARMv7-M (Cortex-M3)

[web at brolinembedded dot se]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55757

Timmy Brolin <web at brolinembedded dot se> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |web at brolinembedded dot
                   |                            |se

--- Comment #7 from Timmy Brolin <web at brolinembedded dot se> 2013-03-02 15:23:11 UTC ---
(In reply to comment #2)
> If you really know that you don't need stack-alignment on an M3, then just
> remove the interrupt attribute.  It really doesn't serve any other purpose on
> M-profile cores other than to cause the stack realignment.

What you suggest requires a change in the C-code depending on the processor.
That is, one piece of C-code will not compile optimally for different Cortex-M3
revisions without modifications to the C-code itself. This is not good for code
which is intended to be used on multiple platforms.


Cortex-M3 r0p0 needs the prologue/epilogue.

Cortex-M3 r1p0 has a new configuration bit called STKALIGN which when enabled
makes the prologue/epilogue unnecessary. (But the default setting is that it
still needs the prologue/epilogue)

Cortex-M3 r2p0 changed the default setting of STKALIGN so that the
prologue/epilogue are unnecessary by default.


I would suggest that the prologue/epilogue should be removed by default when
compiling for r2p0 or higher, but be kept by default for older revisions.
There should also be a compilation switch to manually enable/disable the
prologue/epilogue according to the chosen setting of STKALIGN.

Interrupts can often be time critical, so ISR entry is probably the worst
possible place for extra instructions.