[Bug rtl-optimization/6585] Redundant store/load instruction pairs on ix86

[rask at gcc dot gnu dot org]

------- Comment #16 from rask at gcc dot gnu dot org  2007-11-23 20:43 -------
(In reply to comment #

> I think the bug can be closed as fixed now.

   I'm not so convinced. This part

>	leal    (%ecx,%edx), %esi
>	movl    %esi, %edx
>	movl    4(%esp), %esi

should have been

        addl    %ecx, %edx
        movl    4(%esp), %esi

and using %esi instead of a stack slot doesn't fix the problem. Compare with
what we started with (comment #0):

>	movl    %edx, 4(%esp)       hi+a0*b1          ! Could be simplified
>	addl    %ecx, 4(%esp)       hi+a0*b1+a1*b0    ! to a single insn:
>	movl    4(%esp), %edx                         ! addl %ecx, $edx

The problem hasn't been fixed until we get that "addl %ecx, %edx" instruction.
One more example:
        movl    16(%esp), %eax  ->      movl    16(%esp), %esi
        movl    20(%esp), %esi  ->      movl    20(%esp), %eax
        imull   %ebx, %ecx
        imull   %esi, %eax      ->      imull   %eax, %esi
        addl    %eax, %ecx      ->      addl    %esi, %ecx
        movl    %esi, %eax      ->      -
        mull    %ebx

This is exactly what a register allocator is supposed to figure out: Register
allocation.


-- 

rask at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |REOPENED
         Resolution|FIXED                       |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=6585