[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.
kcook at gcc dot gnu dot org
gcc-bugzilla@gcc.gnu.org
Tue Jan 4 15:06:00 GMT 2005
------- Additional Comments From kcook at gcc dot gnu dot org 2005-01-04 15:06 -------
> (In reply to comment #10)
> Those 0F 6F and 0F 7F are, however, standard MMX instructions. So when you
> use for instance -msse -mfpmath=sse -no-mmx those shouldn't be used as well
> (don't know why would anybody want to do that, but...). However when it is
> used only for copying (as in the example, that I porposed), there are other
> ways, such as using the following instructions:
>
> 0F 12 /r MOVLPS xmm, mem64
> 0F 13 /r MOVLPS mem64, xmm
> 0F 16 /r MOVHPS xmm, mem64
> 0F 17 /r MOVHPS mem64, xmm
If you look at Richard's patch, the compiler will use MOVLPS into XMM register
when only SSE1 is available.
Anders test case now looks like:
mov eax, 19088743 # 54 *movsi_1/1 [length = 5]
mov edx, -1985229329 # 56 *movsi_1/1 [length = 5]
mov DWORD PTR _e64+4, eax # 55 *movsi_1/2 [length = 6]
mov DWORD PTR _e64, edx # 57 *movsi_1/2 [length = 6]
movlps xmm0, QWORD PTR _e64 # 27 *movv2si_internal/11 [length = 7]
movlps QWORD PTR _m64_64, xmm0 # 28 *movv2si_internal/12 [length = 7]
Your test case now won't use SSE at all (reverting to x87 instruction) on an
athlon-xp/pentium3, which I believe is the correct behavior as SSE1 doesn't do
floating point doubles.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235
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