[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

drab at kepler dot fjfi dot cvut dot cz gcc-bugzilla@gcc.gnu.org
Tue Jan 4 15:48:00 GMT 2005


------- Additional Comments From drab at kepler dot fjfi dot cvut dot cz  2005-01-04 15:47 -------
(In reply to comment #16)
> > (In reply to comment #10)
> If you look at Richard's patch, the compiler will use MOVLPS into XMM register
> when only SSE1 is available.

Yes, I noticed. That's good. Thanks. :) 
 
> Your test case now won't use SSE at all (reverting to x87 instruction) on an
> athlon-xp/pentium3, which I believe is the correct behavior as SSE1 doesn't do
> floating point doubles.

It doesn't, but as I said earlier, for copying ANY 64-bit piece of memory (even
doubles) it can be used as well. Perhaps it may not be necessary in the case of
my test code, but I can imagine a situation, where the mmx or st regs. (which
are mapped to the same place AFAIK) will be occupied. Then SSE1 can be used for
copying doubles, even when the interpretation of the data in the xmm reg. is
different. That's just what I wanted to say.


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235



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