[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.
kcook at gcc dot gnu dot org
Mon Jan 3 22:18:00 GMT 2005
------- Additional Comments From kcook at gcc dot gnu dot org 2005-01-03 22:18 -------
(In reply to comment #4)
> I don't have a PIII to test, but http://gcc.gnu.org/ml/gcc/2005-01/msg00114.html
> could be related to this bug.
Your bug though similar is not the same and will need a new PR.
I'm pretty sure Uros's fix is correct for this PR19235.
Your bug comes about because of the movq instruction is attempting to use XMM
registers, but that capability was not added until SSE2. The movq instruction
is being generated from both *movdi_2 and *movv2si_internal in your example.
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