[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

[andersca at gnome dot org]

------- Additional Comments From andersca at gnome dot org  2005-01-03 19:46 -------
Looking at the Intel reference documentation available from ftp://download.intel.com/design/
Pentium4/manuals/25366614.pdf MOVQ has the following opcodes:

0F 6F /r MOVQ mm, mm/m64 Move quadword from mm/m64 to mm. 
0F 7F /r MOVQ mm/m64, mm Move quadword from mm to mm/m64. 
F3 0F 7E MOVQ xmm1, xmm2/m64 Move quadword from xmm2/mem64 to xmm1.
66 0F D6 MOVQ xmm2/m64, xmm1 Move quadword from xmm1 to xmm2/mem64.

and since the two latter instructions are unsupported on AMD and Pentium III you would need some 
other way to move data between the xmm registers and memory. 


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235