[PATCH v3 4/6] bpf: add the load-acquire and store-release instructions
Jose E. Marchesi
jemarch@gnu.org
Mon Oct 12 11:49:44 GMT 2026
Hello Vineet, thanks for the patch.
Nicely picked names for the instructions in normal syntax.
OK for master.
> gas cannot assemble the load-acquire and store-release instructions
> that the kernel has accepted since 6.15 [1] and that clang emits for
> acquire loads and release stores [2]. They are BPF_STX|BPF_ATOMIC
> instructions with imm set to 0x100 (load-acquire) or 0x110
> (store-release), and unlike the other atomics they also come in 8-bit
> and 16-bit sizes.
>
> In normal syntax they are ldacq{b,h,w,dw} and strel{b,h,w,dw}, after
> ldx and stx. Pseudo-C uses the spelling of clang and the kernel:
>
> rd = load_acquire((u64 *)(rs + off))
> store_release((u64 *)(rd + off), rs)
>
> with w registers for the 8, 16 and 32-bit sizes, as clang does. Like
> in clang, they require ISA v4; test that v3 rejects them.
>
> [1] https://git.kernel.org/torvalds/c/880442305a3908589bf4d6fc1d79edb577ee497c
> ("bpf: Introduce load-acquire and store-release instructions")
> [2] https://github.com/llvm/llvm-project/commit/17bfc00f7c4a424d7b5dc6da575865833701fd1a
> ("[BPF] Add load-acquire and store-release instructions under
> -mcpu=v4 (#108636)")
>
> gas/
> * doc/c-bpf.texi (Load-acquire and store-release instructions):
> New subsection.
> * testsuite/gas/bpf/acqrel.s: New test.
> * testsuite/gas/bpf/acqrel.d: New test.
> * testsuite/gas/bpf/acqrel-pseudoc.s: New test.
> * testsuite/gas/bpf/acqrel-pseudoc.d: New test.
> * testsuite/gas/bpf/acqrel-be.d: New test.
> * testsuite/gas/bpf/acqrel-be-pseudoc.d: New test.
> * testsuite/gas/bpf/isa-spec-gated-v3.s: New test.
> * testsuite/gas/bpf/isa-spec-gated-v3.d: New test.
> * testsuite/gas/bpf/isa-spec-gated-v3.l: New test.
> * testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.s: New test.
> * testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.d: New test.
> * testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.l: New test.
> * testsuite/gas/bpf/bpf.exp: Run them.
>
> include/
> * opcode/bpf.h (BPF_IMM32_LDACQ, BPF_IMM32_STREL): Define.
> (enum bpf_insn_id): Add BPF_INSN_LDACQB, BPF_INSN_LDACQH,
> BPF_INSN_LDACQW, BPF_INSN_LDACQDW, BPF_INSN_STRELB,
> BPF_INSN_STRELH, BPF_INSN_STRELW and BPF_INSN_STRELDW.
>
> opcodes/
> * bpf-opc.c (bpf_opcodes): Add entries for load-acquire and
> store-release.
>
> Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>
> ---
> gas/doc/c-bpf.texi | 37 +++++++++++++++++++
> gas/testsuite/gas/bpf/acqrel-be-pseudoc.d | 18 +++++++++
> gas/testsuite/gas/bpf/acqrel-be.d | 18 +++++++++
> gas/testsuite/gas/bpf/acqrel-pseudoc.d | 18 +++++++++
> gas/testsuite/gas/bpf/acqrel-pseudoc.s | 10 +++++
> gas/testsuite/gas/bpf/acqrel.d | 18 +++++++++
> gas/testsuite/gas/bpf/acqrel.s | 10 +++++
> gas/testsuite/gas/bpf/bpf.exp | 6 +++
> .../gas/bpf/isa-spec-gated-v3-pseudoc.d | 4 ++
> .../gas/bpf/isa-spec-gated-v3-pseudoc.l | 5 +++
> .../gas/bpf/isa-spec-gated-v3-pseudoc.s | 7 ++++
> gas/testsuite/gas/bpf/isa-spec-gated-v3.d | 4 ++
> gas/testsuite/gas/bpf/isa-spec-gated-v3.l | 5 +++
> gas/testsuite/gas/bpf/isa-spec-gated-v3.s | 8 ++++
> include/opcode/bpf.h | 5 +++
> opcodes/bpf-opc.c | 26 +++++++++++++
> 16 files changed, 199 insertions(+)
> create mode 100644 gas/testsuite/gas/bpf/acqrel-be-pseudoc.d
> create mode 100644 gas/testsuite/gas/bpf/acqrel-be.d
> create mode 100644 gas/testsuite/gas/bpf/acqrel-pseudoc.d
> create mode 100644 gas/testsuite/gas/bpf/acqrel-pseudoc.s
> create mode 100644 gas/testsuite/gas/bpf/acqrel.d
> create mode 100644 gas/testsuite/gas/bpf/acqrel.s
> create mode 100644 gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.d
> create mode 100644 gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.l
> create mode 100644 gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.s
> create mode 100644 gas/testsuite/gas/bpf/isa-spec-gated-v3.d
> create mode 100644 gas/testsuite/gas/bpf/isa-spec-gated-v3.l
> create mode 100644 gas/testsuite/gas/bpf/isa-spec-gated-v3.s
>
> diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
> index 58d4f01704b5..40254faa5b2b 100644
> --- a/gas/doc/c-bpf.texi
> +++ b/gas/doc/c-bpf.texi
> @@ -908,3 +908,40 @@ compatibility:
> @item xaddw [rd + offset16], rs
> Alias to @code{aadd32}.
> @end table
> +
> +@subsection Load-acquire and store-release instructions
> +
> +These instructions load or store an 8-bit, 16-bit, 32-bit or 64-bit
> +value with acquire or release ordering semantics. The 8-bit, 16-bit
> +and 32-bit loads zero-extend the loaded value into @code{rd}.
> +
> +Note that in pseudoc syntax the 8-bit, 16-bit and 32-bit variants
> +should use @code{w} registers for the loaded or stored value, and the
> +64-bit variants @code{r} registers.
> +
> +@table @code
> +@item ldacqb rd, [rs + offset16]
> +@itemx ldacqh rd, [rs + offset16]
> +@itemx ldacqw rd, [rs + offset16]
> +@itemx ldacqdw rd, [rs + offset16]
> +@itemx wd = load_acquire ((u8 *)(rs + offset16))
> +@itemx wd = load_acquire ((u16 *)(rs + offset16))
> +@itemx wd = load_acquire ((u32 *)(rs + offset16))
> +@itemx rd = load_acquire ((u64 *)(rs + offset16))
> +Load-acquire. Load the value addressed by @code{rs + offset16} into
> +@code{rd}, ordered before any memory access that follows it.
> +
> +@item strelb [rd + offset16], rs
> +@itemx strelh [rd + offset16], rs
> +@itemx strelw [rd + offset16], rs
> +@itemx streldw [rd + offset16], rs
> +@itemx store_release ((u8 *)(rd + offset16), ws)
> +@itemx store_release ((u16 *)(rd + offset16), ws)
> +@itemx store_release ((u32 *)(rd + offset16), ws)
> +@itemx store_release ((u64 *)(rd + offset16), rs)
> +Store-release. Store the value in @code{rs} to the address
> +@code{rd + offset16}, ordered after any memory access that precedes
> +it.
> +@end table
> +
> +These instructions are only available in BPF v4 or later.
> diff --git a/gas/testsuite/gas/bpf/acqrel-be-pseudoc.d b/gas/testsuite/gas/bpf/acqrel-be-pseudoc.d
> new file mode 100644
> index 000000000000..d391a1018a43
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/acqrel-be-pseudoc.d
> @@ -0,0 +1,18 @@
> +#as: -EB -mdialect=pseudoc
> +#objdump: -dr -M dec,pseudoc
> +#source: acqrel-pseudoc.s
> +#name: BPF load-acquire and store-release instructions, pseudoc syntax, big endian
> +
> +.*: +file format .*bpf.*
> +
> +Disassembly of section .text:
> +
> +0+ <.text>:
> + 0: d3 12 00 00 00 00 01 00 w1=load_acquire\(\(u8\*\)\(r2\+0\)\)
> + 8: cb 12 00 02 00 00 01 00 w1=load_acquire\(\(u16\*\)\(r2\+2\)\)
> + 10: c3 12 ff fc 00 00 01 00 w1=load_acquire\(\(u32\*\)\(r2-4\)\)
> + 18: db 12 7f ff 00 00 01 00 r1=load_acquire\(\(u64\*\)\(r2\+32767\)\)
> + 20: d3 12 00 00 00 00 01 10 store_release\(\(u8\*\)\(r1\+0\),w2\)
> + 28: cb 12 00 02 00 00 01 10 store_release\(\(u16\*\)\(r1\+2\),w2\)
> + 30: c3 12 ff fc 00 00 01 10 store_release\(\(u32\*\)\(r1-4\),w2\)
> + 38: db 12 7f ff 00 00 01 10 store_release\(\(u64\*\)\(r1\+32767\),r2\)
> diff --git a/gas/testsuite/gas/bpf/acqrel-be.d b/gas/testsuite/gas/bpf/acqrel-be.d
> new file mode 100644
> index 000000000000..e77789d35f0a
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/acqrel-be.d
> @@ -0,0 +1,18 @@
> +#as: -EB -mdialect=normal
> +#objdump: -dr -M dec
> +#source: acqrel.s
> +#name: BPF load-acquire and store-release instructions, normal syntax, big endian
> +
> +.*: +file format .*bpf.*
> +
> +Disassembly of section .text:
> +
> +0+ <.text>:
> + 0: d3 12 00 00 00 00 01 00 ldacqb %r1,\[%r2\+0\]
> + 8: cb 12 00 02 00 00 01 00 ldacqh %r1,\[%r2\+2\]
> + 10: c3 12 ff fc 00 00 01 00 ldacqw %r1,\[%r2-4\]
> + 18: db 12 7f ff 00 00 01 00 ldacqdw %r1,\[%r2\+32767\]
> + 20: d3 12 00 00 00 00 01 10 strelb \[%r1\+0\],%r2
> + 28: cb 12 00 02 00 00 01 10 strelh \[%r1\+2\],%r2
> + 30: c3 12 ff fc 00 00 01 10 strelw \[%r1-4\],%r2
> + 38: db 12 7f ff 00 00 01 10 streldw \[%r1\+32767\],%r2
> diff --git a/gas/testsuite/gas/bpf/acqrel-pseudoc.d b/gas/testsuite/gas/bpf/acqrel-pseudoc.d
> new file mode 100644
> index 000000000000..f7cef1f6f904
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/acqrel-pseudoc.d
> @@ -0,0 +1,18 @@
> +#as: -EL -mdialect=pseudoc
> +#objdump: -dr -M dec,pseudoc
> +#source: acqrel-pseudoc.s
> +#name: BPF load-acquire and store-release instructions, pseudoc syntax
> +
> +.*: +file format .*bpf.*
> +
> +Disassembly of section .text:
> +
> +0+ <.text>:
> + 0: d3 21 00 00 00 01 00 00 w1=load_acquire\(\(u8\*\)\(r2\+0\)\)
> + 8: cb 21 02 00 00 01 00 00 w1=load_acquire\(\(u16\*\)\(r2\+2\)\)
> + 10: c3 21 fc ff 00 01 00 00 w1=load_acquire\(\(u32\*\)\(r2-4\)\)
> + 18: db 21 ff 7f 00 01 00 00 r1=load_acquire\(\(u64\*\)\(r2\+32767\)\)
> + 20: d3 21 00 00 10 01 00 00 store_release\(\(u8\*\)\(r1\+0\),w2\)
> + 28: cb 21 02 00 10 01 00 00 store_release\(\(u16\*\)\(r1\+2\),w2\)
> + 30: c3 21 fc ff 10 01 00 00 store_release\(\(u32\*\)\(r1-4\),w2\)
> + 38: db 21 ff 7f 10 01 00 00 store_release\(\(u64\*\)\(r1\+32767\),r2\)
> diff --git a/gas/testsuite/gas/bpf/acqrel-pseudoc.s b/gas/testsuite/gas/bpf/acqrel-pseudoc.s
> new file mode 100644
> index 000000000000..3d07f4862ae9
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/acqrel-pseudoc.s
> @@ -0,0 +1,10 @@
> +# Test for load-acquire and store-release instructions
> + .text
> + w1 = load_acquire((u8 *)(r2 + 0))
> + w1 = load_acquire((u16 *)(r2 + 2))
> + w1 = load_acquire((u32 *)(r2 - 4))
> + r1 = load_acquire((u64 *)(r2 + 0x7fff))
> + store_release((u8 *)(r1 + 0), w2)
> + store_release((u16 *)(r1 + 2), w2)
> + store_release((u32 *)(r1 - 4), w2)
> + store_release((u64 *)(r1 + 0x7fff), r2)
> diff --git a/gas/testsuite/gas/bpf/acqrel.d b/gas/testsuite/gas/bpf/acqrel.d
> new file mode 100644
> index 000000000000..a06e5f17f610
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/acqrel.d
> @@ -0,0 +1,18 @@
> +#as: -EL -mdialect=normal
> +#objdump: -dr -M dec
> +#source: acqrel.s
> +#name: BPF load-acquire and store-release instructions, normal syntax
> +
> +.*: +file format .*bpf.*
> +
> +Disassembly of section .text:
> +
> +0+ <.text>:
> + 0: d3 21 00 00 00 01 00 00 ldacqb %r1,\[%r2\+0\]
> + 8: cb 21 02 00 00 01 00 00 ldacqh %r1,\[%r2\+2\]
> + 10: c3 21 fc ff 00 01 00 00 ldacqw %r1,\[%r2-4\]
> + 18: db 21 ff 7f 00 01 00 00 ldacqdw %r1,\[%r2\+32767\]
> + 20: d3 21 00 00 10 01 00 00 strelb \[%r1\+0\],%r2
> + 28: cb 21 02 00 10 01 00 00 strelh \[%r1\+2\],%r2
> + 30: c3 21 fc ff 10 01 00 00 strelw \[%r1-4\],%r2
> + 38: db 21 ff 7f 10 01 00 00 streldw \[%r1\+32767\],%r2
> diff --git a/gas/testsuite/gas/bpf/acqrel.s b/gas/testsuite/gas/bpf/acqrel.s
> new file mode 100644
> index 000000000000..bff2efe7fae0
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/acqrel.s
> @@ -0,0 +1,10 @@
> +# Test for load-acquire and store-release instructions
> + .text
> + ldacqb %r1, [%r2+0]
> + ldacqh %r1, [%r2+2]
> + ldacqw %r1, [%r2-4]
> + ldacqdw %r1, [%r2+0x7fff]
> + strelb [%r1+0], %r2
> + strelh [%r1+2], %r2
> + strelw [%r1-4], %r2
> + streldw [%r1+0x7fff], %r2
> diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp
> index ff148f75dae9..e5a4327e8450 100644
> --- a/gas/testsuite/gas/bpf/bpf.exp
> +++ b/gas/testsuite/gas/bpf/bpf.exp
> @@ -42,12 +42,16 @@ if {[istarget bpf*-*-*]} {
> run_dump_test jump-gotol-cond-pseudoc
> run_dump_test isa-spec-gated
> run_dump_test isa-spec-gated-pseudoc
> + run_dump_test isa-spec-gated-v3
> + run_dump_test isa-spec-gated-v3-pseudoc
> run_dump_test atomic-v1
> run_dump_test atomic
> run_dump_test atomic-pseudoc
> run_dump_test ascast
> run_dump_test ascast-pseudoc
> run_dump_test ascast-v1
> + run_dump_test acqrel
> + run_dump_test acqrel-pseudoc
> run_dump_test indcall-1
> run_dump_test indcall-1-pseudoc
>
> @@ -78,6 +82,8 @@ if {[istarget bpf*-*-*]} {
> run_dump_test atomic-be-pseudoc
> run_dump_test ascast-be
> run_dump_test ascast-be-pseudoc
> + run_dump_test acqrel-be
> + run_dump_test acqrel-be-pseudoc
>
> run_dump_test jump-relax-ja-be
> run_dump_test jump-relax-jump-be
> diff --git a/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.d b/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.d
> new file mode 100644
> index 000000000000..3147adc5b2a4
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.d
> @@ -0,0 +1,4 @@
> +#as: -EL -mdialect=pseudoc -misa-spec=v3
> +#source: isa-spec-gated-v3-pseudoc.s
> +#error_output: isa-spec-gated-v3-pseudoc.l
> +#name: eBPF v4 instructions under ISA spec v3, pseudoc syntax
> diff --git a/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.l b/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.l
> new file mode 100644
> index 000000000000..4b40f32b96df
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.l
> @@ -0,0 +1,5 @@
> +.*: Assembler messages:
> +.*:4: Error: `w1 =load_acquire\(\(u8\*\)\(r2\+0\)\)' requires ISA spec v4 or later
> +.*:5: Error: `r1 =load_acquire\(\(u64\*\)\(r2\+0\)\)' requires ISA spec v4 or later
> +.*:6: Error: `store_release\(\(u16 \*\)\(r1\+0\),w2\)' requires ISA spec v4 or later
> +.*:7: Error: `store_release\(\(u64 \*\)\(r1\+0\),r2\)' requires ISA spec v4 or later
> diff --git a/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.s b/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.s
> new file mode 100644
> index 000000000000..10b3d5687ab6
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/isa-spec-gated-v3-pseudoc.s
> @@ -0,0 +1,7 @@
> + # Likewise for the pseudo-C dialect.
> + .text
> + lock *(u64 *)(r1 + 8) += r2
> + w1 = load_acquire((u8 *)(r2 + 0))
> + r1 = load_acquire((u64 *)(r2 + 0))
> + store_release((u16 *)(r1 + 0), w2)
> + store_release((u64 *)(r1 + 0), r2)
> diff --git a/gas/testsuite/gas/bpf/isa-spec-gated-v3.d b/gas/testsuite/gas/bpf/isa-spec-gated-v3.d
> new file mode 100644
> index 000000000000..d06e9cb0d631
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/isa-spec-gated-v3.d
> @@ -0,0 +1,4 @@
> +#as: -EL -mdialect=normal -misa-spec=v3
> +#source: isa-spec-gated-v3.s
> +#error_output: isa-spec-gated-v3.l
> +#name: eBPF v4 instructions under ISA spec v3, normal syntax
> diff --git a/gas/testsuite/gas/bpf/isa-spec-gated-v3.l b/gas/testsuite/gas/bpf/isa-spec-gated-v3.l
> new file mode 100644
> index 000000000000..720b655ce022
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/isa-spec-gated-v3.l
> @@ -0,0 +1,5 @@
> +.*: Assembler messages:
> +.*:5: Error: `ldacqb %r1,\[%r2\+0\]' requires ISA spec v4 or later
> +.*:6: Error: `ldacqdw %r1,\[%r2\+0\]' requires ISA spec v4 or later
> +.*:7: Error: `strelh \[%r1\+0\],%r2' requires ISA spec v4 or later
> +.*:8: Error: `streldw \[%r1\+0\],%r2' requires ISA spec v4 or later
> diff --git a/gas/testsuite/gas/bpf/isa-spec-gated-v3.s b/gas/testsuite/gas/bpf/isa-spec-gated-v3.s
> new file mode 100644
> index 000000000000..7390351adb75
> --- /dev/null
> +++ b/gas/testsuite/gas/bpf/isa-spec-gated-v3.s
> @@ -0,0 +1,8 @@
> + # Instructions that require ISA v4 must be diagnosed as such
> + # under -misa-spec=v3. aadd is v3 and must still assemble.
> + .text
> + aadd [%r1+8], %r2
> + ldacqb %r1, [%r2+0]
> + ldacqdw %r1, [%r2+0]
> + strelh [%r1+0], %r2
> + streldw [%r1+0], %r2
> diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h
> index 58b6e197e978..a5d59fdd01a8 100644
> --- a/include/opcode/bpf.h
> +++ b/include/opcode/bpf.h
> @@ -164,6 +164,8 @@ typedef uint64_t bpf_insn_word;
> #define BPF_IMM32_AFXOR ((uint64_t)0x000000a1)
> #define BPF_IMM32_AXCHG ((uint64_t)0x000000e1)
> #define BPF_IMM32_ACMP ((uint64_t)0x000000f1)
> +#define BPF_IMM32_LDACQ ((uint64_t)0x00000100)
> +#define BPF_IMM32_STREL ((uint64_t)0x00000110)
>
> /* Unique identifiers for BPF instructions. */
>
> @@ -239,6 +241,9 @@ enum bpf_insn_id
> BPF_INSN_ACMP, BPF_INSN_AXCHG,
> /* Atomic compare-and-swap, atomic exchange (32-bit). */
> BPF_INSN_ACMP32, BPF_INSN_AXCHG32,
> + /* Load-acquire and store-release. */
> + BPF_INSN_LDACQB, BPF_INSN_LDACQH, BPF_INSN_LDACQW, BPF_INSN_LDACQDW,
> + BPF_INSN_STRELB, BPF_INSN_STRELH, BPF_INSN_STRELW, BPF_INSN_STRELDW,
> /* Conditional pseudo-jump "may_goto". A NOP until the BPF runtime
> decides it isn't. */
> BPF_INSN_JCOND,
> diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
> index dfd6e036b738..f070f497f6a7 100644
> --- a/opcodes/bpf-opc.c
> +++ b/opcodes/bpf-opc.c
> @@ -415,6 +415,32 @@ const struct bpf_opcode bpf_opcodes[] =
> {BPF_INSN_AXCHG32, "axchg32%W[ %dr %o16 ], %sr", "%sw = xchg32_32 ( %dr %o16 , %sw )",
> BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXCHG},
>
> + /* Load-acquire and store-release. */
> + {BPF_INSN_LDACQB, "ldacqb%W%dr , [ %sr %o16 ]",
> + "%dw = load_acquire ( ( u8 * ) ( %sr %o16 ) )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_ATOMIC|BPF_IMM32_LDACQ},
> + {BPF_INSN_LDACQH, "ldacqh%W%dr , [ %sr %o16 ]",
> + "%dw = load_acquire ( ( u16 * ) ( %sr %o16 ) )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_ATOMIC|BPF_IMM32_LDACQ},
> + {BPF_INSN_LDACQW, "ldacqw%W%dr , [ %sr %o16 ]",
> + "%dw = load_acquire ( ( u32 * ) ( %sr %o16 ) )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_LDACQ},
> + {BPF_INSN_LDACQDW, "ldacqdw%W%dr , [ %sr %o16 ]",
> + "%dr = load_acquire ( ( u64 * ) ( %sr %o16 ) )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_LDACQ},
> + {BPF_INSN_STRELB, "strelb%W[ %dr %o16 ] , %sr",
> + "store_release ( ( u8 * ) ( %dr %o16 ) , %sw )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_ATOMIC|BPF_IMM32_STREL},
> + {BPF_INSN_STRELH, "strelh%W[ %dr %o16 ] , %sr",
> + "store_release ( ( u16 * ) ( %dr %o16 ) , %sw )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_ATOMIC|BPF_IMM32_STREL},
> + {BPF_INSN_STRELW, "strelw%W[ %dr %o16 ] , %sr",
> + "store_release ( ( u32 * ) ( %dr %o16 ) , %sw )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_STREL},
> + {BPF_INSN_STRELDW, "streldw%W[ %dr %o16 ] , %sr",
> + "store_release ( ( u64 * ) ( %dr %o16 ) , %sr )",
> + BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_STREL},
> +
> /* Old versions of aadd and aadd32. */
> {BPF_INSN_AADD, "xadddw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
> BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
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