[PATCH 1/3] bpf: md: Enable zero_extend{hi, qi}di2 to generate wN regs ...

[Vineet Gupta]

On 3/30/26 12:15 PM, David Faust wrote:
> On 3/29/26 16:17, Vineet Gupta wrote:
>> ... by adjusting the asm template reg string to 'W', similar to commit
>> gbd275e81812c for zero_extendsidi2. However unike that change, this is
>> not a bug fix: zero_extendsidi2 relies on wN reg move to achieve the
>> 32->64 semantics. A {8,16}->64 extension needs to be emulated anyways
>> by masking out extra bits so the reg used is not imp.
>>
>> However wN reg based codegen is still preferable in general:
>>   - It is easier on verifier as it has to track fewer bits and avoids
>>     corner cases which could trip it up for false positives.
>>   - Better native codegen as upper bits are guarateed to be zero and can
>>     leverage target ISA mechanisms to achieve that mostly for free.
>>   - Better nativ codegen on 32-bit targets which need to use 2 regs for
>>     rN regs.
> nit: some typos in the commit message would be good to fix before
> pushing.

Done !

> But the patch itself makes sense and lgtm.
> OK.

Committed !

Thx,
-Vineet