[PATCH v3 2/2] bpf, doc: Improve MOV/MOVSX documentation and add examples
Vineet Gupta
vineet.gupta@linux.dev
Fri Apr 3 16:40:40 GMT 2026
- Add missing form {MOV, K, ALU}.
- Add some assembly (pseudo-C) snippets.
- Rearrange: MOV content comes before MOVSX.
- MOVSX content itself rearranged: canonical sign extension variant
for {8,16,32}-> 64 moved ahead of the special variant which only
sign extends to 32 and zeroes out the upper bits.
- Remove the hyphen '-' in "sign-extension" to make grep hit all
instances with one pattern.
Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>
---
Changes since v2:
- Fixed RST markup for asm example "w5 = w9"
- Added asm example "w5 = (s8)w9" for {MOVSX, X, ALU}
---
.../bpf/standardization/instruction-set.rst | 49 +++++++++++++++----
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/Documentation/bpf/standardization/instruction-set.rst b/Documentation/bpf/standardization/instruction-set.rst
index 96181565906f..863a0cc22a75 100644
--- a/Documentation/bpf/standardization/instruction-set.rst
+++ b/Documentation/bpf/standardization/instruction-set.rst
@@ -414,25 +414,54 @@ etc. This specification requires that signed modulo MUST use truncated division
a % n = a - n * trunc(a / n)
-The ``MOVSX`` instruction does a move operation with sign extension.
-``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into
-32-bit operands, and zeroes the remaining upper 32 bits.
-``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
-operands into 64-bit operands. Unlike other arithmetic instructions,
-``MOVSX`` is only defined for register source operands (``X``).
+For move operations, the ``MOV`` instruction has a few different forms.
+
+``{MOV, X, ALU64}`` means::
+
+ dst = src
+
+e.g. ``r1 = r2``
``{MOV, K, ALU64}`` means::
dst = (s64)imm
-``{MOV, X, ALU}`` means::
+e.g. ``r1 = -4``
+ ``r5 = 9282009``
+
+``{MOV, K, ALU}`` means::
+
+ dst = (u32)imm
+
+e.g. ``w1 = -4``
+ ``w5 = 7302004``
+
+``{MOV, X, ALU}`` has zero extension semantics (upper 32 bits are zeroed)::
dst = (u32)src
+e.g. ``w5 = w9``
+
+The ``MOVSX`` instruction does a move operation with sign extension and has
+a couple of forms.
+
+``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
+operands into 64-bit operands.
+
+e.g. ``r1 = (s8)r2``
+
+The ``{MOVSX, X, ALU}`` form has slightly different semantics: it
+:term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into
+32-bit operands, and zeroes the remaining upper 32 bits (similar to ``MOV``).
+
``{MOVSX, X, ALU}`` with 'offset' 8 means::
dst = (u32)(s32)(s8)src
+e.g. ``w5 = (s8)w9``
+
+Unlike other arithmetic instructions,
+``MOVSX`` is only defined for register source operands (``X``).
The ``NEG`` instruction is only defined when the source bit is clear
(``K``).
@@ -605,7 +634,7 @@ For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the
ABS 1 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_
IND 2 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_
MEM 3 regular load and store operations `Regular load and store operations`_
- MEMSX 4 sign-extension load operations `Sign-extension load operations`_
+ MEMSX 4 sign extension load operations `Sign extension load operations`_
ATOMIC 6 atomic operations `Atomic operations`_
============= ===== ==================================== =============
@@ -649,10 +678,10 @@ instructions that transfer data between a register and memory.
Where '<size>' is one of: ``B``, ``H``, ``W``, or ``DW``, and
'unsigned size' is one of: u8, u16, u32, or u64.
-Sign-extension load operations
+Sign extension load operations
------------------------------
-The ``MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load
+The ``MEMSX`` mode modifier is used to encode :term:`sign extension<Sign Extend>` load
instructions that transfer data between a register and memory.
``{MEMSX, <size>, LDX}`` means::
--
2.53.0
More information about the bpf
mailing list