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- From: Andrew Pinski <pinskia at gmail dot com>
- To: GCC Mailing List <gcc at gcc dot gnu dot org>, Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- Date: Sat, 11 Jan 2020 02:02:27 -0800
- Subject: cortexa57_extra_costs' alu.shift_reg
I was looking into reassoc (for PR 93131) and I noticed that the
alu.shift_reg is set to COSTS_N_INSNS (1). This prevents an
optimization where we combine some if statements into shifts. I
looked into the Corext A57 software optimization guide and saw that
shift with a register has a latency of 1 which is the same as a shift
with an immediate. I looked in the history but it was there to begin
with. Is there a reason for this and would it be acceptable if we
change a57's costs to be correct?
I looked into A65, A72, A75, A76, A77 and N1 software optimization
guides too and they have a similar thing of a latency of one cycle and
those are the ones which use the cortexa57_extra_costs variable too.
Note I could not find the A73 guide though.