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Re: Expansion of narrowing math built-ins into power instructions

Hi Tejas,

On Sat, Aug 10, 2019 at 04:00:53PM +0530, Tejas Joshi wrote:
> +(define_expand "add_truncdfsf3"
> +  [(set (float_extend:DF (match_operand:SF 0 "gpc_reg_operand"))
> +	(plus:DF (match_operand:DF 1 "gpc_reg_operand")
> +		 (match_operand:DF 2 "gpc_reg_operand")))]
> +  "")

float_extend on the LHS is never correct.  I think the following should
work, never mind that it looks like it does double rounding, because it
doesn't (famous last words ;-) ):

(define_expand "add_truncdfsf3"
  [(set (match_operand:SF 0 "gpc_reg_operand")
	  (plus:DF (match_operand:DF 1 "gpc_reg_operand")
		   (match_operand:DF 2 "gpc_reg_operand"))))]

> +(define_insn "*add_truncdfsf3_fpr"
> +  [(set (float_extend:DF (match_operand:SF 0 "gpc_reg_operand" "=<Ff>"))
> +	(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%<Ff>")
> +		 (match_operand:DF 2 "gpc_reg_operand" "<Ff>")))]
> +  "fadd %0,%1,%2"
> +  [(set_attr "type" "fp")])

The constraints should be "f", "%d", "d", respectively.  <Ff> says to
display something for the mode in a mode iterator.  There is no mode
iterator here.  (In what you copied this from, there was SFDF).

You want to output "fadds", not "fadd".

Maybe it is easier to immediately write the VSX scalar version for this
as well?  That's xsaddsp.  Oh, and you need to restrict all of this to
more recent CPUs, we'll have to do some new TARGET_* flag for that I

Finally: please send patches to gcc-patches@ (not gcc@).



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