This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Will backend ever see an memory operand with address wrap around?


Quoting "H.J. Lu" <hjl.tools@gmail.com>:

On Sun, May 13, 2012 at 6:17 PM, <amylaar@spamcop.net> wrote:
Quoting "H.J. Lu" <hjl.tools@gmail.com>:

What is the expect run-time behavior when a + b has
overflow/underflow?


The expectation is wrap-around. ?Note that loop strenght reduction can
cause assumed wrap-around semantics in RTL for strictly conforming C input
where no such wrap-around is in evidence.

I noticed that also. But my impression is loop strength reduction doesn't use wrap-around address for load/store directly.

I've actually seen it for loop strength reduction, but here is an example that does not even involve loop strength reduction to get into trouble - it just involves the distributive law in the indexed access itself:

extern int a[];

void f (int o)
{
  int i;
  for (i = C; i < C + 100; i++)
    {
       a[o-i] = 0;
    }
}

At -O2, gcc (GCC) 4.7.0 20120504 (Red Hat 4.7.0-4) for i686 gives:

f:
.LFB0:
        .cfi_startproc
        movl    4(%esp), %ecx
        movl    $100, %eax
        .p2align 4,,7
        .p2align 3
.L2:
        leal    (%eax,%ecx), %edx
        subl    $1, %eax
        movl    $0, a-1200000400(,%edx,4)
        jne     .L2
        rep
        ret
        .cfi_endproc

Now consider what happens if o == C, and a is within the first GB.
unless the base address is encoded as 64 bit, you'll have an overflow.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]