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Re: GCC 4.7.0 and C++ atomics

On 03/08/2012 11:47 AM, Richard Henderson wrote:
On 03/08/12 00:17, Sebastian Huber wrote:
thanks for the hints. Thus if we want to use the C++ atomic operations on 32-bit ARM in RTEMS we have to implement everything in


and place it in e.g.

Possibly.  It really depends on how rtems attacks the problem of
atomic operations across ARM cpu revisions.  I have no opinion
as to what solution should be used.

I guess similar procedures are required for other architectures.
Not really.  ARM is unique in having an atomic insn (SWP) that
stops working in later ISA revisions, and a required memory
barrier (DMB) introduced late in the ISA revision history that
isn't a backward-compatible NOP.
From a user perspective, you normally only have support
for one architectural variant and all support required
for your application is linked together. RTEMS provides a
single process, multi-threaded POSIX environment and
it is easiest to think of an RTEMS application as a single
program which is statically linked.

RTEMS is generally built multilib and we try to rely on the
architecture flags provided by gcc to be able to handle things
like this.  Do the multilib's match the atomic instruction
support across the various ISA revisions?

If so, it is just a matter of ifdef's to get the right code.

Does arm-eabi have this support? We probably could
just use the same code.


Joel Sherrill, Ph.D.             Director of Research&   Development        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
    Support Available             (256) 722-9985

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