This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: atomicity of x86 bt/bts/btr/btc?


> ;; %%% bts, btr, btc, bt.
> ;; In general these instructions are *slow* when applied to memory,
> ;; since they enforce atomic operation. When applied to registers,
> 
> I haven't found documented confirmation that these instructions are atomic without a lock prefix,
> having checked Intel and AMD documentation and random web searching.
> They are mentioned as instructions that can be used with lock prefix.

They do not automatically lock the bus.  They will lock the bus with the
explicit LOCK prefix, and BTS is typically used for an atomic read/write
operation.

- Rick


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]